1. general description the 74ahc30-q100; 74ahct30-q100 is a high -speed si-gate cmos device and is pin compatible with low-power schottky ttl (l sttl). it is specified in compliance with jedec standard no. 7-a. the 74ahc30-q100; 74ahct30-q100 pr ovides an 8-input nand function. this product has been qualified to the automotive electronics council (aec) standard q100 (grade 1) and is suitable for use in automotive applications. 2. features and benefits ? automotive product qualif ication in accordance with aec-q100 (grade 1) ? specified from ? 40 ? c to +85 ? c and from ? 40 ? c to +125 ? c ? balanced propagation delays ? all inputs have schmitt-trigger actions ? inputs accept voltages higher than v cc ? input levels: ? for 74ahc30-q100: cmos level ? for 74ahct30-q100: ttl level ? esd protection: ? mil-std-883, method 3015 exceeds 2000 v ? hbm jesd22-a114f exceeds 2000 v ? mm jesd22-a115-a exceeds 200 v (c = 200 pf, r = 0 ? ) ? multiple package options 3. ordering information 74ahc30-q100; 74ahct30-q100 8-input nand gate rev. 1 ? 20 november 2013 product data sheet table 1. ordering information type number package temperature range name description version 74ahc30d-q100 ? 40 ? c to +125 ? c so14 plastic small outline package; 14 leads; body width 3.9 mm sot108-1 74ahct30d-q100 74ahc30pw-q100 ? 40 ? c to +125 ? c tssop14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm sot402-1 74ahct30pw-q100 74AHC30BQ-Q100 ? 40 ? c to +125 ? c dhvqfn14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 ? 3 ? 0.85 mm sot762-1 74ahct30bq-q100
74ahc_ahct30_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved . product data sheet rev. 1 ? 20 november 2013 2 of 15 nxp semiconductors 74ahc30-q100; 74ahct30-q100 8-input nand gate 4. functional diagram fig 1. logic symbol fig 2. iec logic symbol mna488 a y 1 8 b 2 c 3 d 4 e 5 f 6 g 11 h 12 8 & mna489 1 2 3 4 5 6 11 12 fig 3. logic diagram b a c d f e g h mna490 y
74ahc_ahct30_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved . product data sheet rev. 1 ? 20 november 2013 3 of 15 nxp semiconductors 74ahc30-q100; 74ahct30-q100 8-input nand gate 5. pinning information 5.1 pinning 5.2 pin description (1) the die substrate is attached to this pad using conductive die attach mate rial. it cannot be used as a supply pin or input. fig 4. pin configuration so14 and tssop14 fig 5. pin configuration dhvqfn14 $ + & |